In modern high-speed electronic systems, pin counts are of high importance. This is the same for memory and CPU/GPU systems. Current DRAM systems offer features such as DBI (DBI=Data Bit Inversion), DM (DM=Data Masking), EDC (EDC=Error Detecting Code); training algorithms, etc. All these features require additional commands and frequently additional pins. Tradeoffs are normally made between performance, additional command complexity, pin count, and implementation complexity. For example, it is possible to provide dedicated DM pins. This enables maximum DM bandwidth, but at the cost of additional pins. Another possibility would be to transmit DM over the normal data pins. This saves pins, but at the cost of data bandwidth, since the data and the DM signal cannot be transmitted in parallel. Moreover, the common complexity is also increased. A further possibility would be to transmit the DM signal over address pins. This allows the DRAM signal to be transmitted parallel to the data, but also introduces new commands, and limits the bandwidth for transmission of the DM signal. In addition, there are normally fewer address pins in comparison to data pins.